CV

Education

Master in Electrical Engineering (VLSI Track)
University of Michigan Ann Arbor (UofM), USA, 8/2022 - 5/2024
- GPA: 3.927
Bachelor of Science in Computer Engineering
University of California San Diego (UCSD), USA, 9/2020 - 6/2022
- GPA: 3.917 (Major GPA: 4.0)
- Warren College Honors community
Bachelor of Science in Computer Engineering and Computer Science
Stony Brook University (SBU), USA, 7/2018 - 8/2020
- GPA: 4.0
- Honor college community

1/2021 - 8/2022: VLSI CAD Lab & WCSNG Lab, UCSD, USA
- Improve HPWL (Half-Perimeter Wire Length) calculator to reduce wire length.
- Enhance cell placement to mitigate pin congestion.
- Design a testing platform for back-scattering BTLE signal ([ISSCC 2022]).
2/2023 - 6/2024: Michigan Integrated Circuit Lab (MICL), UofM, USA
- Implement a Reinforcement Learning capability with new AMS automation tool in OpenFASOC. ([ICCAD 2024], [ISSCC “Code-a-Chip” Travel Grant Awards 2024]).
- Conduct performance analysis of Nvidia confidential computing architecture with large language model like lama using GPGPU simulator.
7/2024 - 2/2025: EIC Lab, Georgia Institute of Technology, USA
- Design micro-architecture and dataflow for the “Freely Interruptible Progressive Large Model Inference Project”.

11/2024 - Present: RTL Design Engineer, RiVAI Technologies, Shenzhen, China
- Micro-architecture and RTL design and implementation for RAS/DEBUG/Die2Die bridge modules.
6/2020 - 6/2021: Software Development Engineer, DHC Software, Nanchang, China
- Design software interfaces and webpages.
- Create organ models using Mimics 20.0 and 3-matic.

Computer Architecture: Out-of-order RISC-V CPU
Programming: C/C++, Python, Java, LaTeX, bash, makefile, Verilog, SystemVerilog
Digital & Physical Design: Synopsys DC/Verdi/PrimeTime, Cadence Innovus